07/31, 13:50–14:25 (Asia/Taipei), TR214
言語: English
Riscduino is a 32 bit RISC V based SOC design targeted to be pin compatible with arudino platform. Multiple version of this SOC design has been tape-out is part of efabless Shuttle program. This project uses only open source tool set for simulation,synthesis and backend tools. The SOC flow follow the openlane methodology and SOC environment is compatible with efabless/carvel methodology.
Key feature of Riscduino SOC
* Open sourced under Apache-2.0 License (see LICENSE file) - unrestricted commercial use allowed.
* Single/Dual/Quad 32 Bit RISC-V core
* 2KB SRAM for instruction cache
* 2KB SRAM for data cache
* 2KB SRAM for Tightly coupled memory - For Data Memory
* Quad SPI Master with 4 Chip select, supports both SPI flash and SRAM interface
* 2 x UART with 16Byte FIFO
* USB 1.1 Host
* I2C Master
* UART Master
* Simple SPI Master with 4 Chip select
* 6 Channel ADC (in Progress)
* 6 x PWM
* 3 x Timer (16 Bit), 1us/1ms/1second resolution
* Pin Compatbible to arudino uno
* Wishbone compatible design
* Written in System Verilog
* Open-source tool set
* simulation - iverilog
* synthesis - yosys
* backend/sta - openlane tool set
* Verification suite provided.
Git Repo Path:
Riscduino Single Core: https://github.com/dineshannayya/riscduino
Riscduino Dual Core: https://github.com/dineshannayya/riscduino_dcore
Riscduino Quad Core: https://github.com/dineshannayya/riscduino_qcore
45 minutes
Proposal Type –Talk (45 mins)
Way to participate –Record participatoin
Target Audience –5 Year Experince
Difficulty –進階
youtube_link –
A open source enthusiast