2022/07/31 –, TR214
言語: English
This talk will introduce NaxRiscv, a recently developed out of order / super-scalar / RISC-V CPU generator and dive in its non-usual hardware elaboration, demonstrating the usefulness of general software technics used as an hardware elaboration tool.
The project is using Scala (A general purpose programming language), SpinalHDL (A Scala hardware generation library) and multiple software patterns, enabling non-intrusive modification and extensions of its CPU design.
NaxRiscv Repository :
https://github.com/SpinalHDL/NaxRiscv
NaxRiscv documentation :
https://spinalhdl.github.io/NaxRiscv-Rtd/main/NaxRiscv/introduction/index.html
Software developper with some hardware design knowledge
Difficulty –中階
youtube_link –
Charles Papon is the initiator and main contributor of a few free and open-source projects: SpinalHDL, A Scala hardware description API (2015). VexRiscv, a RISC-V in-order softcore (linux capable, 2017). SaxonSoc, a framework to build SoC (2020). NaxRiscv : A RISC-V out-of-order superscalar softcore (linux capable, 2021). Since 2020 he has worked full time as an independent, providing community and commercial support for those projects. His background is mixed between hardware and software and got his master degree in industrial systems in 2015.