開源人年會 2022

Riscduino is a 32 bit RISC V based SOC design targeted to be pin compatible with arudino platform. Multiple version of this SOC design has been tape-out is part of efabless Shuttle program. This project uses only open source tool set for simulation,synthesis and backend tools. The SOC flow follow the openlane methodology and SOC environment is compatible with efabless/carvel methodology.