Gaëtan LOUNES
3rd year+ PhD student at IRISA (Institute for Research in Computer Science and Random Systems) interested in compilers, MLIR and FPGA.
Session
08-13
15:00
30min
Julia meets (again) the FPGA : Higher-level synthesis methodology for heterogeneous hardware and software architectures
Gaëtan LOUNES
The modular compiler of Julia allows non-standard compilation flows and heteregeneous targets. Field Programmable Gate Array (FPGAs) are one of them, and Julia is an excellent fit for High-Level Synthesis (HLS). We present an HLS toolchain that takes advantage of the MLIR tracing system Reactant.jl and CIRCT HLS flow. This approach enables flexible design-space exploration and rapid prototyping of FPGA designs.
Julia, GPUs, and Accelerators
Room 3