JuliaCon 2026

Julia meets (again) the FPGA : Higher-level synthesis methodology for heterogeneous hardware and software architectures
2026-08-13 , Room 3

The modular compiler of Julia allows non-standard compilation flows and heteregeneous targets. Field Programmable Gate Array (FPGAs) are one of them, and Julia is an excellent fit for High-Level Synthesis (HLS). We present an HLS toolchain that takes advantage of the MLIR tracing system Reactant.jl and CIRCT HLS flow. This approach enables flexible design-space exploration and rapid prototyping of FPGA designs.


Julia has achieved excellent results in non-standard compilation flows, notably because of the modularity of its toolchain. Flexible middle-end and back-end enables, for instance, automatic differenciation with Enzyme.jl or heteregeneous target with GPUCompiler.jl such as GPUs. Field Programmable Gate Arrays (FPGAs) are another interesting accelerator, as they are used in high-throughput and energy efficient contexts.

Configurate FPGAs usually involves using a Hardware Description Language (HDL), but they require solid hardware knowledge. High Level Synthesis (HLS) has therefor been introduced to fill the gap between software paradigms and HDLs. Several HLS approaches have been developed in the Julia ecosystem [1,2,3].
State-of-the-art HLS tools, such as Vitis HLS, used a Domain-Specific Language (DSL) based on C++; it is handle by a custom Clang front-end to produce an LLVMIR which is used by the HLS engine. This IR is not ideal because of it low level nature: Multi-Layer IR (MLIR) [4] have been used instead.

There are two classes of MLIR front-ends:
- static ones, which translate JuliaIR to an MLIR representation, they work by matching semantics (type system, 1/0-indexing) between JuliaIR and MLIR dialects. Notably, only a subset of Julia programs can be handled, for instance, type stability is required. Based on Brutus.jl, both [2] and [3] develop a custom MLIR front-end for HLS purpose, they differ in the choosen HLS engine. [2] uses ScaleHLS [5] which is a framework build on top of VitisHLS. [3] uses a MLIR based HLS engine proposed by CIRCT [6].

  • dynamic ones, the idea is to generate a MLIR program from an execution trace. This method targets higher-level dialect which handle tensor semantics. Reactant.jl [7] is an example of such a tracing approach. Unlike static methods, contraints on the Julia program are less strict, and this flexibily fit nicely to the Julia ecosystem.

In a similar approach to Hardware.jl, we propose an HLS toolchain based on CIRCT HLS that takes advantage of the Reactant.jl tracing system. We use the flexibily of the Julia compiler to create mechanisms that enable high-level design-space exploration for HLS. In particular, this presentation focuses on numerical applications and their use by hardware accelerators, in particular, showing the interest of Julia for rapid prototyping.

[1] B. Biggs, I. McInerney, E. C. Kerrigan, and G. A. Constantinides, High-level Synthesis using the Julia
Language, Feb. 2022. arXiv: 2201.11522 [cs].

[2] G. Lounes, R. Gerzaguet, M. Gautier, Flexible front-end for high-level synthesis leveraging heterogeneous compilation, Jan. 2025.

[3] B. Short, I. McInerney, J. Wickerson, A High-level Synthesis Toolchain for the Julia Language, Dec. 2025. arXiv: 2512.15679 [cs]

[4] C. Lattner, M. Amini, U. Bondhugula, et al., MLIR: A Compiler Infrastructure for the End of Moore’s
Law, Feb. 2020. arXiv: 2002.11054 [cs].

[5] H. Ye, C. Hao, J. Cheng, et al., ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level
Intermediate Representation, Dec. 2021. arXiv: 2107.11673 [cs].

[6] https://github.com/llvm/circt

[7] https://github.com/EnzymeAD/Reactant.jl

3rd year+ PhD student at IRISA (Institute for Research in Computer Science and Random Systems) interested in compilers, MLIR and FPGA.