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SUMMARY:FastIce.jl: a massively parallel ice flow model running on GPUs - 
 Ludovic Räss\, Samuel Omlin\, Mauro Werder\, Ivan Utkin
DTSTART;TZID=Europe/Amsterdam:20240710T170000
DTEND;TZID=Europe/Amsterdam:20240710T173000
DTSTAMP:20260815T010850Z
UID:pretalx-juliacon2024-VHFAQ8@pretalx.com
DESCRIPTION:We introduce [FastIce.jl](https://github.com/PTsolvers/FastIce
 .jl)\, a novel ice flow model for massively parallel architectures\, writt
 en in Julia. Leveraging GPUs (Nvidia\, AMD) and supporting distributed com
 puting through MPI.jl\, FastIce.jl includes a thermo-mechanically coupled 
 Full-Stokes ice flow model. We present the performance testing of FastIce.
 jl in single-node and distributed scaling benchmarks on LUMI\, the largest
  European supercomputer.
LOCATION:For Loop (3.2)
URL:https://pretalx.com/juliacon2024/talk/VHFAQ8/
END:VEVENT
BEGIN:VEVENT
SUMMARY:Seamless transition from single-core Python to Julia Multi-GPU - S
 amuel Omlin
DTSTART;TZID=Europe/Amsterdam:20240712T144400
DTEND;TZID=Europe/Amsterdam:20240712T150600
DTSTAMP:20260815T010850Z
UID:pretalx-juliacon2024-N779AY@pretalx.com
DESCRIPTION:We present a new approach to transition seamlessly and with un
 precedented effectiveness from a single-CPU-core Python prototype to a Jul
 ia application that is deployable on distributed GPUs. During porting of t
 he Python prototype to Julia\, the approach enables concurrent interactive
  stepwise execution of both codes and systematic verification almost line 
 by line.
LOCATION:Function (4.1)
URL:https://pretalx.com/juliacon2024/talk/N779AY/
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SUMMARY:Sustainable Development of Stencil-based HPC Applications - Ludovi
 c Räss\, Samuel Omlin\, Ivan Utkin
DTSTART;TZID=Europe/Amsterdam:20240712T155000
DTEND;TZID=Europe/Amsterdam:20240712T160000
DTSTAMP:20260815T010850Z
UID:pretalx-juliacon2024-QLVPSN@pretalx.com
DESCRIPTION:We present a successful approach for a sustainable development
  of stencil-based HPC applications in Julia. The approach includes automat
 ic performance optimization for hardware-agnostic high-level kernels\, dat
 a layout abstractions enabling memory layouts optimized per backend\, and 
 GPU-aware inter-process communication that is automatically hideable behin
 d computation. We demonstrate on multiple examples near optimal performanc
 e and scaling on thousands of GPUs.
LOCATION:Else (1.3)
URL:https://pretalx.com/juliacon2024/talk/QLVPSN/
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