Gaëtan LOUNES
2nd year PhD student at IRISA (Institute for Research in Computer Science and Random Systems) interested in compilers and FPGA.
Session
07-10
19:30
30min
Julia meets Field Programmable Gate Array (FPGA)
Gaëtan LOUNES
Julia has achieved strong result in heterogeneous compilation such as GPU or IPU. But little work has been carried out for Field Programmable Gate Array (FPGA). Although Julia language with its type system, readability and libraries is an excellent fit for High-Level Synthesis (HLS). The idea is to used Julia IR as a MLIR frontend, develop a new toolchain which can generate representation usable by MLIR HLS tools such as ScaleHLS.
Posters
Else (1.3)