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UID:pretalx-juliacon2024-RJEPZY@pretalx.com
DTSTART;TZID=CET:20240710T193000
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DESCRIPTION:Julia has achieved strong result in heterogeneous compilation s
 uch as GPU or IPU. But little work has been carried out for Field Programm
 able Gate Array (FPGA). Although Julia language with its type system\, rea
 dability and libraries is an excellent fit for High-Level Synthesis (HLS).
  The idea is to used Julia IR as a MLIR frontend\, develop a new toolchain
  which can generate representation usable by MLIR HLS tools such as ScaleH
 LS.
DTSTAMP:20260618T104252Z
LOCATION:Else (1.3)
SUMMARY:Julia meets Field Programmable Gate Array (FPGA) - Gaëtan LOUNES
URL:https://pretalx.com/juliacon2024/talk/RJEPZY/
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