2021年8月1日 –, TR313
語言: English
The efabless Caravel project---Chip design, democratized
hackmd url:https://hackmd.io/@coscup/HJjKEpPRu/%2F%40coscup%2FSyYOVavAu
演講摘要:Efabless has teamed up with Google and SkyWater foundry to make silicon hardware design fully open source, available to everyone, and achievable by anyone with sufficient motivation and a basic background in software but not necessarily hardware. We leverage the open-source Sky130 CMOS process and open-source EDA tools to make chip design free of NDAs or licensing costs. We have developed the Caravel "harness" chip, a pre-defined framework around a 10mm^2 area that is available for supporting user-defined projects. The framework is an open-source github project and provides a RISC-V microcontroller and padframe. Instructions show in detail how to take any RTL system description and synthesize, simulate, and verify a hardware design within the Caravel chip framework using free and open source tools. We have streamlined the manufacture submission process to a few online forms and automated checks. We have successfully completed the first multi-project wafer run with forty designs from users of all backgrounds from software to hardware, and experience from novice to expert, and have scheduled two more such runs for this year. Successful open-source projects can be folded back into the Caravel design to make each successive shuttle
run better and easier for the user. In this talk, we will describe how we have democratized chip design, and how you can ride this wave to realize your dream of turning your ideas into working silicon.
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英文演講摘要:Efabless has teamed up with Google and SkyWater foundry to make silicon hardware design fully open source, available to everyone, and achievable by anyone with sufficient motivation and a basic background in software but not necessarily hardware. We leverage the open-source Sky130 CMOS process and open-source EDA tools to make chip design free of NDAs or licensing costs. We have developed the Caravel "harness" chip, a pre-defined framework around a 10mm^2 area that is available for supporting user-defined projects. The framework is an open-source github project and provides a RISC-V microcontroller and padframe. Instructions show in detail how to take any RTL system description and synthesize, simulate, and verify a hardware design within the Caravel chip framework using free and open source tools. We have streamlined the manufacture submission process to a few online forms and automated checks. We have successfully completed the first multi-project wafer run with forty designs from users of all backgrounds from software to hardware, and experience from novice to expert, and have scheduled two more such runs for this year. Successful open-source projects can be folded back into the Caravel design to make each successive shuttle
run better and easier for the user. In this talk, we will describe how we have democratized chip design, and how you can ride this wave to realize your dream of turning your ideas into working silicon.
Software engineers, FPGA developers, hobbyists, students, and others who are interested in turning ideas into circuit chips.
內容難易度:中階
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