07-10, 19:30–20:00 (Europe/Amsterdam), Else (1.3)
Julia has achieved strong result in heterogeneous compilation such as GPU or IPU. But little work has been carried out for Field Programmable Gate Array (FPGA). Although Julia language with its type system, readability and libraries is an excellent fit for High-Level Synthesis (HLS). The idea is to used Julia IR as a MLIR frontend, develop a new toolchain which can generate representation usable by MLIR HLS tools such as ScaleHLS.
Julia has achieved excellent results in the field of heterogeneous compilation, attributed to the flexibility of the compilation toolchain. This is further enhanced by the extension of the compiler through GPUCompiler.jl, enabling smooth targeting of GPU or IPU. Each target defines a new LLVM pipeline tailored to its specific requirements, generating specialized LLVM Intermediate Representation (IR). Field Programmable Gate Arrays (FPGA) are other interesting targets [1], as they focus on energy efficiency and high-throughput contexts.
Programming FPGAs traditionally involves using Hardware Description Language (HDL), but this approach is suboptimal due to its reliance on solid hardware knowledge and unwieldy algorithm development. High-Level Synthesis (HLS) has been introduced to address these limitations. State-of-the-art HLS tools, such as Vitis from AMD, employ a Design-Specific Language (DSL) based on C, which is then transformed into LLVM IR using a custom Clang frontend. The LLVM IR contains hardware semantics in the form of various annotations, utilized and transformed by the HLS backend to generate HDL code, such as Verilog or VHDL.
While the approach leveraging the Vitis design suite is interesting, it has limitations, particularly due to the closed-source nature of the LLVM IR usage, making integration with new frontends cumbersome. An alternative method employed by many HLS users avoids the direct use of DSL or LLVM IR; instead, they introduce a new toolchain using Multi-Layer IR (MLIR) [2]. MLIR generalizes the concept of IR and its manipulation, introducing new IRs (referred to as dialects in MLIR terminology), which are analyzed and transformed to fit an IR sent to HLS tools.
In a manner similar to the Brutus prototype tool, we propose using Julia IR as an MLIR frontend. The key distinction with Brutus lies in the application of MLIR not to enhance backend compilation but to integrate with state-of-the-art HLS MLIR toolchains such as ScaleHLS [3]. Notably, we aim to leverage Julia IR singularities, such as typed IR or compactness, and incorporate these semantics into MLIR. To achieve this goal, several mandatory changes to the Julia compiler are necessary, including modifying the inliner policy and developing a new toolchain using MLIR with an original dialect. The toolchain for translating Julia IR to MLIR standard dialects is actively being developed, and the compilation stack will be open-sourced and proposed as a tool to the community. This enables the possibility to write Julia application that will run on specific FPGA target.
References:
[1] B. Biggs, I. McInerney, E. C. Kerrigan, and G. A. Constantinides, High-level Synthesis using the Julia
Language, Feb. 2022. arXiv: 2201.11522 [cs].
[2] C. Lattner, M. Amini, U. Bondhugula, et al., MLIR: A Compiler Infrastructure for the End of Moore’s
Law, Feb. 2020. arXiv: 2002.11054 [cs].
[3] H. Ye, C. Hao, J. Cheng, et al., ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level
Intermediate Representation, Dec. 2021. arXiv: 2107.11673 [cs].
2nd year PhD student at IRISA (Institute for Research in Computer Science and Random Systems) interested in compilers and FPGA.